The present invention relates to motor controllers and more particularly to a method and an apparatus for compensating for switching device voltage losses and switching device dynamics losses in inverter systems.
One type of commonly designed motor is a three phase motor having three Y-connected stator windings. In this type of motor, each stator winding is connected to an AC voltage source by a separate supply line, the source providing time varying voltages across the stator windings. Often, an adjustable speed drive (ASD) will be positioned between the voltage source and the motor to control motor speed by controlling the stator voltages and frequency.
Many ASD configurations include a pulse width modulated (PWM) inverter consisting of a plurality of switching devices. Referring to FIG. 1, an exemplary PWM inverter leg 10 corresponding to one of three motor phases includes two series connected switches 12, 13 between positive and negative DC rails 18, 19 and two diodes 16, 17, a separate diode in inverse parallel relationship with each switch 12, 13. By turning the switches 12, 13 ON and OFF in a repetitive sequence, leg 10 receives DC voltage via rails 18 and 19 and provides high frequency voltage pulses to a motor terminal 22 connected to a stator winding 24. By firing the switching devices in a regulated sequence the PWM inverter can be used to control both the amplitude and frequency of voltage that is provided across winding 24.
Referring to FIG. 2, an exemplary sequence of high frequency voltage pulses 26 that an inverter might provide to a motor terminal can be observed along with an exemplary low frequency alternating fundamental or terminal voltage 28 and related alternating current 30. By varying the widths of the positive portions 32 of each high frequency pulse relative to the widths of the negative portions 34 over a series of high frequency voltage pulses 26, a changing average voltage which alternates sinusoidally can be generated. The changing average voltage defines the terminal voltage 28 that drives the motor. The terminal voltage 28 in turn produces a low frequency alternating current 30 that lags the voltage by a phase angle "PHgr".
The hardware that provides the firing pulses to the PWM inverter is typically referred to as a PWM signal generator. Among other things, a PWM generator typically includes a comparator that receives at least one modulating signal or waveform and a carrier signal/waveform for comparison. Referring to FIG. 3a, exemplary modulating and carrier waveforms used by a signal generator to generate the firing pulses for leg 10 are illustrated. As well known in the art, a carrier waveform 36 is perfectly periodic and operates at what is known as a carrier frequency. A modulating voltage waveform 38 generally and ideally is sinusoidal, having a much greater period than carrier waveform 36.
Referring also to FIGS. 3b and 3c, an ideal upper signal 40 and an ideal lower signal 42 generated by a PWM generator comparing the signals of FIG. 3a and that may control the upper and lower switches 12, 13, respectively, are illustrated. The turn-on times tu1 and tu2 and turn-off times to1, to2 of the upper and lower signals 40, 42, respectively, come from the intersections of the modulating waveform 38 and the carrier waveform 36. When the modulating waveform 38 intersects the carrier waveform 36 while the carrier waveform has a positive slope, the upper signal 40 goes OFF and lower signal 42 goes ON. On the other hand, when the modulating waveform 38 intersects the carrier waveform 36 while the carrier waveform has a negative slope, the upper signal 40 goes ON and the lower signal 42 goes OFF. Thus, by comparing the carrier waveform 36 to the modulating waveform 38, the states of the upper and lower signals 40, 42, respectively, can be determined.
While the modulating and carrier signals are referred to as waveforms in order to simplify understanding of this explanation, in reality, each of the waveforms is a digital count that represents a corresponding waveform. For instance, the modulating waveform may be converted into a count that oscillates within a range between a first or minimum modulating count equal to or greater than zero and a second or maximum modulating count. Where the modulating waveform is sinusoidal, the modulating count changes in a sinusoidal time-varying fashion indicative of the waveform. For instance, where the minimum count is zero, a carrier count oscillates in a linear time varying fashion from zero to a maximum carrier count Tcmax (see FIG. 3a) that is equal to or greater than the maximum modulating count and back to zero during each carrier cycle. The comparator compares the modulating count with the carrier count and when the modulating count is greater than the carrier count, causes the corresponding upper and lower switches to be turned ON and OFF, respectively, and when the modulating count is less than the carrier count, causes corresponding upper and lower switches to be turned OFF and ON, respectively. Because the modulating count value determines the ratio of switch ON times to PWM period duration (i.e., carrier cycle period), the modulating often is converted to percent of the carrier period Ts and referred to as a duty cycle.
When the duty cycle count is less than one-half, the resulting terminal voltage is negative because the corresponding lower switch is ON for more than half the PWM period. Similarly, when the duty cycle count is greater than one-half, the resulting terminal voltage is positive because the corresponding upper switch is ON for more than half the PWM period.
Referring also to FIGS. 2 and 3d, an ideal high frequency voltage pulse 26 resulting from the ideal upper and lower signals 40, 42 in FIGS. 3b and 3c that might be provided at terminal 22 can be observed. When the upper signal 40 is ON and the lower signal 42 is OFF, switch 12 allows current to flow from the high voltage rail 18 to motor terminal 22 thus producing the positive phase 44 of pulse 26 at motor terminal 22. Ideally, when the upper signal 40 goes OFF and the lower signal 42 goes ON, switch 12 immediately turns OFF and switch 13 immediately turns ON connecting motor terminal 22 and the low voltage rail 19 producing the negative phase 46 of pulse 26 at terminal 22. Thus, the ideal high frequency voltage pulse 26 is positive when the upper signal 40 is ON and is negative when the lower signal 42 is ON. Also, ideally, the low frequency terminal voltage and corresponding current (see FIG. 2) should completely mirror the modulating waveforms.
Unfortunately, these ideal switch operating conditions do not occur as there are several switch and inverter operating phenomenon that cause terminal voltage distortions. For example, one problem with PWM inverters has been that the high frequency terminal voltage pulses (see 26 in FIG. 2) cause ripple in the resulting low frequency phase voltages and currents. This ripple distortion has generally been addressed by either providing line filters that tend to smooth the ripple or by adopting faster switching technology. Elaborate filters are bulky and expensive and therefore are not preferred. Current inverter switching technology has advanced rapidly and modern switches are now capable of changing state in as little as several tens of nano-seconds (e.g., 50 nsec.). For this reason, recent inverter designs have typically adopted high speed switching configurations to reduce ripple distortion.
One other relatively well understood and therefore, not surprisingly, generally well compensated distortion phenomenon, is referred to as inverter switch delay. Control schemes for compensating for switch delays are generally referred to as deadtime compensation (DTC) schemes. Exemplary DTC schemes are described in U.S. Pat. No. 5,811,949 and U.S. Pat. No. 5,917,721.
While switch delays and ripple distortion are well understood and DTC and other schemes have been developed that generally minimize terminal current and voltage distortion due to turn on delays and ripple, unfortunately, experience has shown that even after DTC has been implemented and fast switching technology has been adopted, terminal voltages and currents still include appreciable distortion.
To this end, referring to FIG. 4, a terminal current is illustrated that was generated with a 10 hp industrial drive with full DTC, with a load cable of approximately 3 meters, with a 2 Hz modulating frequency and a 2 kHz carrier frequency. Clearly, under these conditions, terminal current distortion is minimal. However, referring also to FIG. 5, the terminal current in FIG. 5 was generated using the same configuration used to generate the waveform of FIG. 4, albeit with the carrier frequency increased to 8 kHz. Clearly the increased carrier frequency results in excessive and unacceptable distortion. Referring also to FIG. 6, a terminal current is illustrated where, except for the load cable length being extended from 3 meters to 60 meters, the configuration and operating conditions (i.e., carrier and modulating frequencies) used to generate the waveform is the same as that used to generate the waveform of FIG. 5. In FIG. 6 the current distortion is even greater with the longer cable and the waveform includes an appreciable DC offset.
While various general theories have been advanced to explain the distortions illustrated in FIGS. 5 and 6, a relatively incomplete understanding of the sources of these distortions has lead to inaccurate compensation. For instance, some industry members have incorrectly characterized these other distortions as the result of imperfect DTC. In these cases, where attempts have been made to mitigate these other distortions, only relatively crude methods have been adopted. For instance, one solution has been to simply adjust the DTC of a system to tune a system for operation under specific operating conditions. While commissioning of this type can accommodate specific operating characteristics (e.g. current levels, temperature, duty cycles, etc.), if the operating characteristics are altered, this solution again results in terminal voltage distortions and may, in some cases, increase the distorting affects.
One other solution to compensate for distortion not eliminated via DTC has been to provide relatively expensive fast sampling sensors and complex software architecture in one or more feedback loops. While possible in high end drive systems, unfortunately, in standard drives, such hardware and software is typically cost prohibitive.
In other cases where the sources have been recognized as generally related to interaction between inverter components and other system components (e.g., capacitive/inductive cables, loads, etc.), some industry members have recognized a correlation between the degree of distortion and switch turn-on and turn-off times. Thus, it has generally been recognized that the distortions in FIGS. 5 and 6 increase as the inverter switch turn-on and turn-off times decrease (i.e., as faster switches are used to configure the inverter). Recognizing the adverse effects of such high switching speeds, despite some of the advantages (e.g., terminal voltage ripple reduction) associated with fast switching technology, there has been a shift back toward adopting slower switching technology to reduce distortion. To this end, several next generation inverter configurations are being designed with relatively slow switching devices (e.g., devices having switching times on the order of 200 nsec.) as opposed to faster devices (e.g., devices having 50 nsec. switching times).
Thus, it would be advantageous to have a system that decreases terminal voltage distortion relatively inexpensively and that enables use of fast switching technology without causing excessive distortion.
It has been recognized that, the sources of distortion in FIGS. 5 and 6 can be identified and their effects quantified so that relatively accurate and automated compensation can be implemented to inexpensively minimize terminal voltage distortion. To this end, and more specifically, it has been recognized that, in addition to turn on delay related distortion, there are two other de-couplable general sources of distortion including purely device related distortion and distortion related to how devices operate and interact with other inverter components as a function of specific operating characteristics. The purely device related distortion is referred to herein as xe2x80x9cdevice dropxe2x80x9d error (Vdde) while distortion related to how devices operate/interact with other components is referred to as xe2x80x9cdevice dynamicsxe2x80x9d error (Vdye).
Device drop error Vdde generally includes distortion due to the intrinsic shortcomings of the devices used to configure a control system. For instance, every electronic device has a specific voltage drop associated therewith which, over the course of several thousands of pulses, adds up to cause an appreciable terminal voltage error. It has been determined that the device voltage drop within each leg of an inverter is not constant but rather varies is a function of current magnitude, current direction, device temperature, device structure and switch states (i.e., ON or OFF).
Device dynamics error Vdye includes distortion that results from interaction of inverter bridge devices and other system components linked thereto such as load supply cables, loads and other capacitive coupling that occurs within an inverter configuration. Generally, Vdye is a function of current magnitude and direction.
To compensate for each of Vdde and Vdye the present invention provides a Vdde compensator and a separate Vdye compensator. The Vdde and Vdye compensators are independent of a dedicated DTC compensator although they compensate in a similar fashion. For instance, each of the compensators generates a duty cycle correction count that is used to alter the carrier signal count thereby generating a desired PWM output.
The Vdde compensator is programmed to take into account the operating characteristics that affect the voltage drop across inverter devices including device temperature, duty cycle, device structure and phase current magnitude and direction. Typically, device drop data may be obtained from device manufacturers or in some cases, may be determined during a commissioning procedure.
The Vdye compensator is programmed to take into account the operating characteristics that affect system related distortion including phase current magnitude and direction as well as duty cycle. Various values required to program the Vdye compensator are generated during a commissioning procedure.
Consistent with the above the invention includes an apparatus for mitigating distortion at the output terminals of a multi-phase inverter drive system linked via supply lines to a load wherein the system includes an inverter and an inverter controller, the inverter including a plurality of switches that link positive and negative DC buses to the lines at output terminals, the controller receiving modulating signals and carrier signals and comparing the modulating signals and the carrier signals to generate firing pulses to control the switches, the inverter characterized by device drop losses and the system, load and lines characterized by device dynamics losses that cause terminal current distortion, device errors including both device drop and device dynamics losses, the apparatus comprising, for each phase: a device compensator receiving system phase current signals and, based on the received current signals, generating a device error compensation signal and a summer receiving the phase modulating signal and the device error compensation signal and mathematically combining the modulating signal and error signal to generate a compensated modulating signal, the summer providing the compensated modulating signal to the controller for comparison to the carrier signal.
In one aspect the invention further includes, for each phase, a dead time compensator that generates a dead time compensation error signal se that is provided to the summer, the summer, mathematically combining the dead time compensation signal, the modulating signal and the device error signal for the phase to generate the compensated modulating signals.
In one embodiment the device compensator includes both a device drop compensator and a device dynamics compensator and the device error signal includes both a device drop error and a device dynamics error signal, the summer, for each phase, mathematically combining each of the modulating signal, the device drop error signal, the device dynamics error signal and the dead time compensation error signal to generate the compensated modulating signals.
In some embodiments the controller generates a duty cycle count for each phase and the device drop compensator receives the cycle count and generates a device drop error signal as a function of both the current signals and the cycle count. Here, the device dynamics compensator may receive the cycle count and generate the device dynamics error signal as a function of both the current signals and the cycle count.
The invention may also include a temperature module that determines the temperature of the inverter devices and provides a temperature signal to the device drop compensator, the device drop compensator generating the device drop error signal as a function of the temperature signal, the current signal and the cycle count. The phase current signals may be either feedback load current signals or command signals.
In one embodiment the device compensator includes a device drop compensator, for each phase, the controller generates a duty cycle count indicating the percent Txcex1/Ts of a carrier cycle Ts during which the phase is linked to the positive DC rail, the inverter includes a switch and inverse parallel diode bridge and the device drop error signal Vdde determined by solving the following equations, where i greater than 0: Vdde=(Ta/Ts)(xe2x88x92Vigbt)+(1xe2x88x92Ta/Ts)(xe2x88x92Vdiode), and, where i less than 0: Vdde=(Ta/Ts)(Vdiode)+(1xe2x88x92Ta/Ts)(Vigbt), where Vdiode is the voltage drop across a conducting diode and Vigbt is the voltage drop across a conducting switch. Here, when iu greater than 0 the summer adds the device drop error Vdde=(Ta/Ts)(xe2x88x92Vigbt)+(1xe2x88x92Ta/Ts)(xe2x88x92Vdiode) to the modulating signal and where iu less than 0 the summer adds the device drop error Vdde=(Ta/Ts)(Vdiode)+(1xe2x88x92Ta/Ts)(Vigbt) to the modulating signal.
In some embodiments the device compensator includes a device dynamics compensator and the dynamics compensator determines the dynamics error signal by solving the following equations: where Ithresh greater than iu greater than 0: Vdye=f(|iu|) else, where xe2x88x92Ithresh less than iu less than 0: Vdye=xe2x88x92f(|iu|), where f(|iu|) is a device dynamics correction function of the inverter/load. Ithresh is the threshold current below which the correction function is activated. It has been determined that above a certain current level Ithresh the device dynamic compensation is not necessary to provide good results. For instance, in one exemplary system Ithresh may be 10-40% (likely 20-30%) of the rated current for a specific system and may be set either at a factory or during a commissioning procedure. In other embodiments the Ithresh value may be the rated current level for a given system so that the device dynamics compensation, while only minimally effective at high currents, would essentially be active at all times. The correction function may be a polynomial, multiple line segments, or linear. For a linear approximation f(|iu|) becomes: f(|iu|)=K(Ithreshxe2x88x92|iu|). Here, when iu greater than 0 the summer subtracts the device dynamic error from the modulating signal and where iu less than 0 the summer adds the device dynamic error to the modulating signal.
In some embodiments the controller generates a carrier count that counts back and forth between a minimum number and a maximum number and the dynamics compensator determines the dynamics error signal by solving the following equations, where the carrier count is counting up: where Ithresh greater than iu greater than 0: Vdye=K(Ithreshxe2x88x92|iu|) else, where iu less than 0: Vdye=Ton and where the carrier counter is counting down: where iu greater than 0: Vdye=Ton, else, where Ithresh less than iu less than 0: Vdye=xe2x88x92K(Ithreshxe2x88x92|iu|). When the counter is counting up, the device dynamics compensator subtracts the device dynamics error from the modulating signal and when the counter is counting down the device dynamics compensator adds the device dynamics error to the modulating signal.
The invention further includes methods to perform many of the processes described above in conjunction with the inventive apparatus.
These and other objects, advantages and aspects of the invention will become apparent from the following description. In the description, reference is made to the accompanying drawings which form a part hereof, and in which there is shown a preferred embodiment of the invention. Such embodiment does not necessarily represent the full scope of the invention and reference is made therefore, to the claims herein for interpreting the scope of the invention.